An increase in the sampling rate of analog-to-digital conversion may be achieved by the use of composite ADCs. A composite ADC contains a number of interleaved sub-ADCs with a common input and a sequential timing. If the number of sub-ADCs equals N, then the resulting conversion rate is N times larger than the rate of one sub-ADC.
Each sub-ADC incorporated in a composite ADC has its own amplitude frequency response and phase frequency response. The misalignment of amplitude and phase frequency responses of different sub-ADCs causes specific signal distortions, with the appearance of spurious frequency components being of prime importance.
The main way to prevent the appearance of the specific distortions in a composite ADC is to use equalization of its output digital signal. There are several patents concerned with digital equalization of a composite ADC output signal, for example U.S. Pat. No. 5,239,299, U.S. Pat. No. 7,408,495, US Patent Application Publication Nos. US 2005/0151679, US 2010/0182174, and others. The equalizer in these patents is an FIR filter (or a set of FIR filters), with the samples coming from each of sub-ADCs being corrected with equalizer coefficients that are calculated from the frequency responses of this sub-ADC.
The ADC equalizer is built usually as a conventional Finite Impulse Response (FIR) filter. The most resource consuming components of FIR filter are multipliers. As the equalizer length L may reach several hundreds of taps, the required number of multipliers becomes the main reason that makes it necessary to use in the equalizer design, more FPGAs and/or FPGAs of bigger size.
It is well known in the art that there is a need for reducing the number of multipliers in FIR filters by using more effective algorithms. There are different approaches to the solution of this problem. One that is most successful and most suitable for digital equalizer design was developed in the works of S. Winograd, Z. Mou and P. Duhamel.
The digital equalizer, like any FIR filter, forms its output sample by calculating a convolution between the input samples and equalizer coefficients. The Winograd-Mou-Duhamel algorithm reduces the number of multiplication in convolution calculation by using, at each clock cycle, some intermediate calculation results obtained in the preceding cycle.
A digital equalizer for an interleaved ADC is a time variant device. The equalizer coefficients that are used at a current clock cycle depend on responses of the correspondent sub-ADC and are different from coefficients used in the previous cycle. For this reason, the Winograd-Mou-Duhamel algorithm, as it is, cannot be directly used to reduce the multipliers number in an ADC digital equalizer.
The present technology provides a digital equalizer for an interleaved ADC that performs equalization of the frequency responses with a reduced number of multipliers.